Reducing LUT Count for FPGA-Based Mealy FSMs

Alexander Barkalov,Kazimierz Krzywicki,Larysa Titarenko

doi:10.3390/app10155115

Abstract

Very often, digital systems include sequential blocks which can be represented using a model of Mealy finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and power consumption. The paper proposes a novel design method optimizing LUT counts of LUT-based Mealy FSMs. The method is based on simultaneous use of such methods of structural decomposition as the replacement of FSM inputs and encoding of the collections of outputs. The proposed method results in three-level logic circuits of Mealy FSMs. These circuits have regular systems of interconnections. An example of FSM synthesis with the proposed method is given. The experiments with standard benchmarks were conducted. The results of experiments show that the proposed approach leads to reducing the LUT counts from 12% to 59% in average compared with known methods of synthesis of single-level FSMs. Furthermore, our approach provides better LUT counts as compared to methods of synthesis of two-level FSMs (from 9% to 20%). This gain is accompanied by a small loss of FSM performance.

Highlights

One of the features of our time is a wide application of digital systems in various spheres of human activity [1,2]
The number of look-up table (LUT) inputs is rather small [10,12]. This feature leads to the need of functional decomposition of systems of Boolean functions (SBFs) representing finite state machine (FSM) circuits [17,18]. This leads to multi-level FSM circuits with complex systems of interconnections [9]
The FSM U6 is based on the encoding of collections of outputs (Figure 12b)

Summary

Introduction

One of the features of our time is a wide application of digital systems in various spheres of human activity [1,2]. The number of LUT inputs is rather small [10,12] This feature leads to the need of functional decomposition of systems of Boolean functions (SBFs) representing FSM circuits [17,18]. The internal occupied resources consumed by a LUT-based FSM circuit include LUTs, flip-flops, interconnections, circuit of synchronization, input-output blocks. The complexity of FPGA-based projects is constantly growing [9] To overcome this contradiction, it is necessary to develop the methods of technology mapping that take into account rather small value of LUT’s inputs. The main contribution of this paper is a novel design method aimed at reducing the number of LUTs in circuits of FPGA-based Mealy FSMs. The proposed approach is based on joint usage of two known methods of structural decomposition (replacement of inputs and encoding of collections of outputs).

Specifics of FPGAs and Mealy FSMs

State of the Art

Main Idea of the Proposed Method

Example of Synthesis

Experimental Results

Conclusions