Reducing library development cycle time through an optimum layout create flow

Abstract

One of the major roadblocks in reduction of library generation cycle time is the layout generation phase. The two methods of doing automatic layout generation are synthesis and migration. The tools that are available for layout generation, each have it's own limitations. This paper describes how we have developed an integrated methodology for generating standard cell layouts using synthesis and migration. The placement engine of the synthesis tool was replaced by the Simulated Annealing based placer as well as the routing engine of the synthesis tool was made more intelligent and robust by using our own algorithms. The migration flow was also enhanced to suit requirements that were specific to ASIC cell libraries. This paper also presents the strategy we developed of an optimum combination of synthesis and migration for reducing the cycle time for generation of cell layouts. This strategy has enabled us to remove the bottleneck of the layout generation cycle time. The paper also touches upon how we have extended the flow to handle the "what-if" experiments that are carried out at a library definition phase.