Reducing cross-coupling among interconnect wires in deep-submicron datapath design

Abstract

As CMOS technology enters the deep submicron design era, the lateral inter-wire coupling capacitance becomes the dominant part of load capacitance and makes RC delay on the bus structures very data-dependent. Reducing the capacitance is crucial for achieving high-speed as well as lower power operation. In this paper, we propose two interconnect layout design methodologies for minimizing the cross-coupling effect in the design of full-custom datapath. Firstly, we describe the control signal ordering scheme which was shown to minimize the switching power consumption by 10% and wire delay by 15% for a given set of benchmark examples. Secondly, a track assignment algorithm based on evolutionary programming was used to minimize the capacitance. Experimental results have shown that chip performance improvement of as much as 40% can be obtained using the proposed interconnect schemes in various stages of the datapath layout optimization.