Reduced-memory forward-backward check node processing architecture for non-binary LDPC decoding

Abstract

When the code length is moderate, non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than their binary counterparts at the cost of higher decoding complexity. The check node processing is a major bottleneck of NB-LDPC decoding. Its computation complexity can be reduced by an iterative forward-backward scheme. Nevertheless, large memory is required in this scheme to store intermediate results. In this paper, a novel check node processing scheme and corresponding VLSI architectures are proposed for the Min-max NB-LDPC decoding. The proposed scheme first sorts out a limited number of the most reliable input messages. Then the forward and backward processes are carried out using only these messages. In addition, an innovative approach is developed to derive the output messages from only a small number of intermediate results without noticeable performance loss. Accordingly, both the memory requirement and computation complexity are greatly reduced. For an example (837, 726) NB-LDPC code over GF(25), our proposed check node processing architecture can achieve at least 34% area reduction and about the same throughput compared to previous efforts based on the original forward-backward scheme.