Reduced rank photonic computing accelerator

Abstract

Use of artificial intelligence for tasks such as image classification and speech recognition has started to form an integral part of our lives. Facilitation of such tasks requires processing a huge amount of data, at times in real time, which has resulted in a computation bottleneck. Photonic cores promise ultra-fast convolutional processing by employing broadband optical links to perform parallelized matrix–vector multiplications (MVMs). Yet the scalability of photonic MVMs is limited by the footprint of the system and energy required for programming the weights, which scale with the matrix dimensionality (M×N). One approach is to reduce the number of hardware matrix weights required, which would allow for less aggressive scaling of the hardware. In this paper, we propose and experimentally demonstrate precisely such a hardware photonic architecture with reduced rank of operation, significantly improving on scalability and decreasing the system complexity. We employ the reduced photonic matrix with reconfigurable optical weights in image processing tasks where we demonstrate the ability to achieve edge detection and classification with 33% reduction in the conventional 3×3 kernel matrix and with no detectable loss of accuracy. While our demonstration is in photonics, this architecture can be universally adapted to MVM engines, and offers the potential for fast, scalable computations at a lower programming cost.