Reduced‐order small signal modelling of high‐order high step‐up converters with clamp circuit and voltage multiplier cell

Abstract

Generally, the modelling of high step-up converters with a large number of passive components consisting of inductors, coupled-inductors (CL) and capacitors is very complex. Recently, to further increase the voltage gain in high step-up converters in a simple and low-cost manner, voltage multiplier (VM) circuits have been increasingly used. Also, to reduce the switch voltage spike, clamp circuits are applied. This leads to an increase in the order of systems and operational modes as well. Thus, for simpler modelling and reducing the state variables, the use of reduced-order techniques are required. A general structure for small signal modelling of such converters including passive clamp, CL and VM circuits is presented. For this purpose, an example of these types of converters is selected. At first, a full-order model of this high-order converter is derived using the state-space averaging method. Then, two reduced-order models of the converter are derived and then compared with the full-order model. Also, the small signal and low frequency behaviour is evaluated. In addition, the impact of the parameter variations on the frequency response and stability margin is investigated. Finally, experimental results based on laboratory prototype are presented to verify the validity of the theoretical analysis.