Reduced ground bounce and improved latch-up suppression through substrate conduction

Abstract

The conventional method of bond wiring V/sub ss/ pads on CMOS chips is examined. For p-type epitaxial CMOS on a p/sup +/ substrate, these V/sub ss/ pads may not be required. Instead, the conduction path would be through the substrate to the ground plane on the package. This technique reduces the ground bounce and improves latch-up suppression. Furthermore, for input/output (I/O) bound chips, the substrate conduction method reduces the size of the I/O frame, reduces cost by decreasing die size, and improves performance by reducing conductor lengths on the chip. An ADVICE comparison was performed between the conventional and substrate conduction methods for connection V/sub SS/ to a CMOS chip in 0.9- mu m technology. Results of packaged-chip measurements are also presented. >