Reduced Device Count Asymmetrical Multilevel Inverter Topology Using Different PWM Techniques

Abstract

This paper presents a new topology in a multilevel inverter (MLI) field with reduce device count and less number of dc voltage source with different PWM technique. This Proposed topology offers high power capability associated with less commutation losses, less total harmonic distortion (THD). For a specific number of levels in output, proposed topology required less switching components and DC voltage sources in comparison of Conventional topologies. This topology used asymmetric voltage sources is in nature, that required three asymmetric voltage sources and eight switching devices for producing 15-Level single phase output voltage. This topology is simple and optimal, which can be easily extended for higher level in output voltage of multilevel inverter. This paper presents the comparison of total harmonic distortion, with different pulse width modulation technique, with different modulation index, and the simulation result of proposed topology for single phase 15-level multilevel inverter, which are carried out by using MATLAB/Simulink R2013a software version.