Abstract
Image stitching describes the process of reconstruction of a high-resolution image by combining multiple images. Using a scanning electron microscope as the image source, individual images will show patterns in a nm dimension, whereas the combined image may cover an area of several mm2. The recovery of the physical layout of modern semiconductor products manufactured in advanced technologies nodes down to 22 nm requires a perfect stitching process with no deviation with respect to the original design data, as any stitching error will result in failures during the reconstruction of the electrical design. In addition, the recovery of the complete design requires the acquisition of all individually layers of a semiconductor device. The layers represent a 3D structure with interconnections defining error limits on the stitching error for each individual scanned image mosaic. An advanced stitching and alignment process is presented, enabling a true geometrical layout recovery in nanoscale dimensions, which is also applied to and evaluated for other use cases from biological applications.
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