Reconfigured test architecture optimization for TSV-based three-dimensional SoCs

Abstract

The technology of three-dimensional (3D) SoCs is emerging as a promising approach for extending Moore’s Law. Managing test architecture design and optimization of 3D integration are crucial challenges. In this paper, we propose a reconfigured test architecture optimization for 3D SoCs, including a novel scheme to minimize the pre-bond test time and Known-Good Stack (KGS) test to guarantee the yield of 3D SoCs. Experimental results on ITC’02 SoC benchmark circuits show that our scheme reduces the total test time by around 23% on average and nearly 30% in maximum compared with one baseline solution.