Reconfiguration of VLSI arrays: a technique for increased flexibility and reliability

Abstract

The problem afforded is that of dynamic reconfiguration of regular arrays of processing elements, implemented as VLSI devices; the aim is that of achieving high production yield and reliability, while keeping on-chip redundancy as low as possible and maintaining such figures of merit as design regularity and interconnection locality. The basic approach considered is that of a set of redundant “busses” cotrolled by a regular pattern of switches; such structure has been already proposed by other authors to achieve reconfiguration for error patterns belonging to a fairly large class, but previous proposals required a relevant redundancy in terms of spare processing elements (for a rectangular array, redundancy increased with n 2, given an n *n array. We prove that use of global algorithms — rather than of purely local ones — allows to achieve again survival again survival to large classes of fault patterns, with much lower redundancy (increasing with the order of n). A structure with interconnection grids formed by sets of three busses along each direction, will be presented: it will be seen that two alternative algorithms — of increasing complexity and efficiency — can utilize it. A simple preliminary solution for the switch will be suggested.