Reconfiguration Cost for Reconfigurable Computing Architectures

Abstract

Reconfigurable computing systems show the advantage of high flexibility and high-performance or low-power relative to traditional computing systems. Reconfiguration can change user logic statically or dynamically. The reconfiguration is a key feature in the reconfigurable computing system, however, the reconfiguration techniques are not considered enough. One of the reconfiguration techniques must be chosen for usage target characteristics of reconfiguration. This article shows the cost of typical reconfiguration techniques which can be applied to not only field-programmable gate arrays (FPGAs) but also coarse-grained reconfigurable arrays (CGRAs). We call these microarchitectures, field-programmable logic (FPL). We focus on three device classes; traditional configurable FPL (ex. FPGA), a partially reconfigurable FPL and a multi-context FPL. We investigate how the size and frequency of reconfiguration can be taken care of and how much speed-up is theoretically expected from a perspective of reconfiguration cost. In addition, the investigation introduces temporal and spatial configuration cache techniques.