Reconfigurable Systolic 2D-Arrays of Bit-Level Processor Elements for High Speed Data Processing in Embedded Computer Systems

Abstract

High-speed data processing provided by special-purpose processors is one of the basic directions in the development of real-time computer systems. The paper is devoted to reconfigurable processors that may be represented as 2D-arrays containing bit-level processor elements. Special-purpose architectures of these processors may be preferable for real-time computations with strong restrictions of computation time or hardware costs. One of the significant features of 2D-arrays is maximal concurrency for data stream processing. But this requires adaptation of arbitrary algorithms to 2D-architecture. This is one of the most difficult problems in modern computer science; its successful solution determines the efficiency of 2D-architectures application in real-time systems. Some problems connected with the theory of computation by means of reconfigurable 2D-arrays of bit-level processor elements are discussed. Moreover, some results of research and development of the one specific processor array (MiniTera-2) for air- and space-born applications are presented.