Reconfigurable scan chains: A novel approach to reduce test application time

Abstract

A major drawback in using scan techniques is the long test application times needed to shift test data in and out of a device. This paper presents a novel methodology based on reconfiguring a single scan chain to minimize the shifting time in applying test patterns to a device. The main idea is to employ multiplexers to bypass registers that are not frequently accessed in the test process and hence reduce the overall test time. For partitioned scan designs, we describe two different modes of test application which can be used to efficiently tradeoff the logic and routing overheads of the reconfiguration strategy with the test application time. In each case, we provide optimization techniques to minimize the number of added multiplexers and the corresponding test time. Implementation results demonstrate test time reductions as large as 75% over traditional test schemes at the expense of 1-3 multipliers.