Reconfigurable missile‐borne SAR imaging SoC design

Abstract

With the rapid development of the integrated circuit manufacturing technology and the radar technology, the demand for miniaturisation, low power consumption, and real-time performance of synthetic aperture radar (SAR) imaging system is becoming higher and higher. By designing reconfigurable IP cores and configuring parameters through CPU, a reconfigurable missile-borne SAR imaging SoC chip based on IP reuse is designed to meet this urgent demand. Using 0.13μm CMOS process, the SoC chip has been taped out and verified successfully. Compared with the traditional ‘DSP + FPGA’ platform, this chip can ensure the real-time performance of the missile-borne SAR imaging system and has more advantages in scale and power consumption.