Reconfigurable Memory Module in the RAMP System for Stream Processing

Abstract

A memory module with logic to support random access (RAM), FIFO access (FIFO), delay line implementation (DELAY), and lookup table implementation (LUT) is described in this chapter. The memory module can be reconfigured statically to be in one of the four modes (RAM, FIFO, DELAY, LUT) and is part of a system containing reconfigurable clusters of memory and processors, called RAMP. Each cluster in RAMP has a memory module, four computation processors, and an I/O processor that communicate using a handshake protocol. The memory module uses a self-timed memory array with separate data lines for read and write. The memory array consists of rows of memory cells and a dummy row circuit that mimics the worst case delay in accessing the memory. This dummy circuit generates a done signal when read/write has been completed.