Reconfigurable Inner Product Hardware Architecture for Increased Hardware Utilization in SDR Systems

Abstract

Most digital signal processing (DSP) algorithms for multimedia and communication applications require multiplication and addition operations. Especially matrix-matrix or matrix-vector the multiplications frequently used in DSP implementations needs inner product arithmetic which takes the most processing time. Also multiplications for the DSP algorithms for software defined radio (SDR) applications require different input bitwidths. Therefore, the multiplications for inner product need to be sufficiently flexible in terms of bitwidths to utilize hardware resources efficiently. This paper proposes a novel reconfigurable inner product architecture based on a pipelined adder array, which offers increased flexibility in bitwidths of input arrays. The proposed architecture consists of sixteen 4 × 4 multipliers and a pipelined adder array and can compute the inner product of input arrays with any combination of multiples of 4 bitwidths such as 4 x 4,4 × 8, 4 x 12,... 16 x 16. Experimental results show that the proposed architecture has latency of maximum 9 clock cycles and throughput of 1 clock cycle for inner product of various bitwidths of input arrays. When TSMC 0.18 μm libraries are used, the chip area and critical path of the proposed architecture are 186,411 gates and 2.79 ns, respectively. The proposed architecture can be applied to a reconfigurable arithmetic engine for real-time SDR system designs.