Reconfigurable computing for space-time adaptive processing

Abstract

Space-time adaptive processing (STAP) refers to a class of signal processing techniques used to process returns of an antenna array radar system. STAP algorithms are designed to extract desired target signals from returns comprised of Doppler shifts, ground clutter, and jamming interference. STAP simultaneously and adaptively combines the signals received on multiple elements of an antenna array-the spatial domain-and from multiple pulse repetition periods-the temporal domain. The output of STAP is a weighted sum of multiple returns, where the weights for each return in the sum are calculated adaptively and in real-time. The most computationally intensive portion of most STAP approaches is the calculation of the adaptive weight values. Calculation of the weights involves solving a set of linear equations based on an estimate of the covariance matrix associated with the radar return data. Existing approaches for STAP typically rely on the use of multiple digital signal processors (DSPs) or general-purpose processors (GPPs) to calculate the adaptive weights. These approaches are often based on solving multiple sets of linear equations and require the calculation of numerous vector inner products. This paper proposes the use of FPGAs as vector coprocessors capable of performing inner product calculation. Two different inner-product co-processor designs are introduced for use with the host DSP or GPP. The first has a multiply-and-accumulate structure, and the second uses reduction-style tree structure having two multipliers and an adder.