Reconfigurable CMOS SPAD imagers for time of flight imaging and LIDAR

Abstract

Technologies for manufacturing CMOS SPAD arrays are advancing rapidly towards dense nanoscale technologies accompanied by backside illumination and 3D stacking. This talk will review recent milestones in integrated CMOS SPAD sensors in academia and industry. The growing ecosystem of in-house and foundry manufacturing technologies underpinning these devices will be described. New opportunities for innovation have been created by these platforms in particular the ability to integrate complex digital signal and image processing close to the detectors. To illustrate this potential we will describe two recently developed CMOS SPAD arrays implementing multiple reconfigurable imaging modalities and show how the modalities can be conveniently combined to improve performance and create new capabilities. The first device is a 3D-stacked 90nm/40nm 256x256 imaging array for flash LIDAR with high dynamic range intensity and 3D time of flight modalities at reconfigurable spatial, distance and time scales. The second device is a 128x128 40nm CMOS front-side illuminated array with column parallel image processing implementing dynamic-vision and 3D time of light modes. Both devices employ on chip coarse histogramming to reduce I/O rates which have held back SPAD array imagers from achieving dynamic range compatible with outdoor background light levels. The intelligent conjunction of these imaging modalities (facilitated by the innate digital processing of SPAD imagers) will be shown to enable power and data rate reduction whilst achieving high dynamic range and image resolution.