Reconfigurable Architecture of UFMC Transmitter for 5G and Its FPGA Prototype

Abstract

A universal-filtered multicarrier (UFMC) system that is a generalization of filtered orthogonal frequency-division multiplexing (OFDM) and filter-bank-based multicarrier is being considered as a potential candidate for fifth-generation due to its robustness against intercarrier interference as in cyclic-prefix-based OFDM systems. However, real-time hardware realization of multicarrier systems is limited by a large number of arithmetic units for inverse fast Fourier transform and pulse-shaping filters. In this paper, we aim to propose a low-complexity and reconfigurable architecture for a baseband UFMC transmitter. To the best of our knowledge, the proposed architecture is the first reconfigurable architecture that has the flexibility to choose the number of subcarriers in a subband without any change in hardware resources. In addition, the proposed architecture selects the filter from a group of filters with a single selection line. Moreover, we use a commercially available field-programmable gate array device for real-time testing and analyzing the baseband UFMC signal. From the extensive experiments, we study the occupied bandwidth, main-lobe power, and sidelobe power of the baseband signal with different filters in real-time scenarios. Finally, we measure the quantization error in baseband signal generation for the proposed UFMC transmitter architecture and find comparable with the error bound.