Reconciliation of different gate-voltage dependencies of 1/f noise in n-MOS and p-MOS transistors

Abstract

We have examined the 1/f noise of 3 /spl mu/m/spl times/16 /spl mu/m, n- and p-MOS transistors as a function of frequency (f), gate-voltage (V/sub g/) and temperature (T). Measurements were performed for 3 Hz/spl les/f/spl les/50 kHz, 100 mV/spl les/|V/sub g/-V/sub th/|/spl les/4 V, and 77 K/spl les/T/spl les/300 K, where V/sub th/ is the threshold voltage. Devices were operated in strong inversion in their linear regimes. At room temperature we find that, for n-MOS transistors, S(V/sub d/)/spl prop/V/sub d//sup 2//(V/sub g/-V/sub th/)/sup 2/, and for p-MOS transistors, we generally find that S(V/sub d/)/spl prop/V/sub d//sup 2//(V/sub g/-V/sub th/, consistent with trends reported by others. At lower temperatures, however, the results can be very different. In fact, we find that the temperature dependence of the noise and the gate-voltage dependence of the noise show similar features, consistent with the idea that the noise at a given T and V/sub g/ is determined by the trap density, D/sub t/(E), at trap energies E=E(T,V/sub g/). Both the T- and V/sub g/-dependencies of the noise imply that D/sub t/(E) tends to be constant near the silicon conduction band edge, but increases as E approaches the valence band edge. It is evidently these differences in D/sub t/(E) that lead to differences in the gate-voltage dependence of the noise commonly observed at room temperature for n- and p-MOS transistors.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>