Abstract
Contemporary hardware implementations of artificial neural networks face the burden of excess area requirement due to resource-intensive elements such as multiplier and non-linear activation functions. The present work addresses this challenge by proposing a resource-efficient Co-ordinate Rotation Digital Computer (CORDIC)-based neuron architecture (RECON) which can be configured to compute both multiply-accumulate (MAC) and non-linear activation function (AF) operations. The CORDIC-based architecture uses linear and trigonometric relationships to realize MAC and AF operations respectively. The proposed design is synthesized and verified at 45nm technology using Cadence Virtuoso for all physical parameters. Implementation of the signed fixed-point 8-bit MAC using our design, shows 60% less area, latency, and power product (ALP) and shows improvement by 38% in area, 27% in power dissipation, and 15% in latency with respect to the state-of-the-art MAC design. Further, Monte-Carlo simulations for process-variations and device-mismatch are performed for both the proposed model and the state-of-the-art to evaluate expectations of functions of randomness in dynamic power variation. The dynamic power variation for our design shows that worst-case mean is $189.73\mu W$ which is 63% of the state-of-the-art.
Highlights
A N ARTIFICIAL neural network (ANN) has been a game-changer in computing paradigms within the last decade
We propose a Resource Efficient Coordinate Rotation Digital Computer (CORDIC)-based neuron architecture (RECON) that provides compelling application opportunities and enables efficient yet configurable computations required in a neural networks
We demonstrate how Co-ordinate Rotation Digital Computer (CORDIC) is configured within RECON to operate in linear or hyperbolic rotation mode to solve arithmetic and trigonometric operations respectively
Summary
A N ARTIFICIAL neural network (ANN) has been a game-changer in computing paradigms within the last decade. An area and power-efficient configurable architecture are desirable at all technology nodes [11] Keeping this in mind, we propose a Resource Efficient Coordinate Rotation Digital Computer (CORDIC)-based neuron architecture (RECON) that provides compelling application opportunities and enables efficient yet configurable computations required in a neural networks. The proposed logic has two benefits– Firstly, it is scalable in terms of area and power as a single block can compute both MAC and activation function. We propose a CORDIC-based design of an unsigned/signed computational unit which can compute both MAC and non-linear activation function.
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