Recessed source/drain for sub-50 nm UTB SOI MOSFET

Abstract

In this work, the recessed source/drain (ReS/D) ultra-thin body (UTB) SOI MOS transistor is investigated in detail. Results reveal that the ReS/D structure provides UTB devices with much lower source/drain series resistance than the elevated source/drain (E-S/D) one and thereby alleviates the critical requirement for low contact resistivity of sub-50 nm generations. On the other hand, the ReS/D devices do not exhibit the degraded short channel effect immunity compared to the E-S/D devices. The design guidelines and window for the ReS/D devices are also suggested in terms of the simulation results. It is thus demonstrated that the ReS/D approach is capable of accelerating SOI device scaling down to 10 nm node.