Abstract
Recently a number of breakthroughs have been reported by our team in the component qualities of transistors built on Carbon Nanotube (CNT) channels. However, any emerging channel material which seeks to outperform established semiconductors for transistor logic applications has a substantial hill to climb, given the incredible capabilities of advanced Si-based logic technology platforms. This talk will first aim to frame our progress on Carbon Nanotube CMOS technology in the broader context of the value proposition and desired component qualities needed to realize practical impact in computing applications. Next, we will share advances in the fundamental building blocks for Carbon Nanotube transistors towards these targets including channel, contact, doping, and gate-stack modules. Finally we will describe new record CNT MOSFET performance milestones achieved by integrating best available device components for first time, which gives insight into the remaining performance limiters and future directions.[1] G. Pitner, et al., "Building High Performance Transistors on Carbon Nanotube Channel," VLSI 2023.[2] S. Li, et al., "High-Performance and Low Parasitic Capacitance CNT MOSFET: 1.2 mA/um at Vds of 0.75 V by self-aligned doping in sub-20 nm spacer," IEDM 2023.[3] N. Safron, et al., "Low N-type Contact Resistance to Carbon Nanotubes in Highly Scaled Contacts through Dielectric Doping," IEDM 2023.[4] H.-Y. Chiu, et al., "Self-Aligned Contact Doping for Performance Enhancement of Low-Leakage Self-Alignment Method for High-Density Aligned CNT Array," Advanced Materials Interfaces, 2023.[5] T.A. Chao, et al., "Small Molecule Additives to Suppress Bundling in Dimensional-Liminted Self-Alignment Method for High-Density Aligned CNT Array," Advanced Materials Interfaces, 2023.[6] Q. Lin, et al., " Band-to-Band Tunneling Leakage Current Characterization and Projection in Carbon Nanotube Transistors," ACS Nano 2023.[7] Z. Zhang, et al., "Complementary Carbon Nanotube Metal-Oxide-Semicondcutor Field-Effect Transistors with Localized Solid-State Extension DOping," Nature Electronics, 2023.[8] S.K. Su, et al., " Perspective on Low-Dimensional Channel Materials for Extremely Scaled CMOS," VLSI 2022.[9] Z. Zhang, et al., "Sub-Nanometer Interfacial Oxides on Highly Oriented Pyrolytic Graphite and Carbon Nanotubes Enabled by Lateral Oxide Growth," ACS Applied aterials & Interfaces, 2022.[10] G. Pitner, et al., "Sub-0.5 nm Interfacial Dielectrics Enables Superior Electrostatics: 65 mV/dec top-gated Carbon Nanotube FETs at 15 nm gate length," IEDM 2020.
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