Reasoning about the function and timing of integrated circuits with interval temporal logic

Abstract

Important aspects of behavior at the transistor level are discussed, including timing and capacitance. In the approach described here, the structures of circuits and their functional behavior are described with interval temporal logic (ITL). These specifications are expressed in Prolog, and the logical manipulations of the proof process are achieved with the Prolog system. To demonstrate the flexibility of this approach, the behavior of several CMOS circuits designed with different design styles is described. These examples include a dynamic latch and a 1-b adder, both of which use a two-phase clocking scheme and exploit charge storage. The 1-b adder is a sophisticated full adder implemented with a dynamic CMOS design style. Timing as well as functional aspects of behavior are derived, and constraints on the way a circuit interacts with its environment are reasoned about formally. >