Real-time stereo video decoding and rendering on multi-core architecture

Abstract

With the production of 3D movies like `Avatar', demand for 3D content has seen enormous growth. With the development of advanced display and capturing technologies, 3D has become popular now a day. In this paper, techniques to implement stereo video (H.264/MVC coded) decoding and rendering on dual-core processors have been described. Depending on the type of display techniques used to display 3D video, different 3D formats are used to appropriately render it. E.g. Anaglyph for 2D screen, side by side, top bottom, checker board (DLP), frame sequential for 3D TVs. Format conversion is implemented as a post processing module and final 3D format data is fed to the device. Format conversion and rendering is also a cycle consuming task which is independent of video decoding. We here propose to decode the stereo video on one core and rendering and format conversion on the other core of a dual-core processor. Proposed idea has been implemented on Intel dual core architecture and on OMAP4 platform having ARM Cortex-A9 dual core processor. Results show that total decoding and rendering time can be brought closer to decoding time using dual core architecture under assumption that decoding time is greater than the rendering time which is the case generally.