Abstract
In order to solve the conflict between high-speed digital image processing system and real-time performance, this paper designs a high-speed image processing unit with real-time camera link interface. Which is combined with multiple DSPs and Field Programmable Gate Arrays (FPGA). Then this unit and DDR SDRAM dynamic random access memory chip together constitute a high-speed camera real-time image storage system. This paper focuses on the basic composition of the system, high-speed data interface, data buffering and storage design. By processing 500 frames per second of high-speed digital images of 8-bit 1280×1024 pixels, the experiment proves that the system design meets the needs of high-speed image real-time processing and storage.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
