Abstract
This paper discusses the use of restructurable hardware, specifically field programmable gate arrays, in real-time image processing and manipulation tasks such as convolution filtering, scaling and rotation, composition, color space transformation, etc. Each of these functions can be implemented using a customized pipeline design to obtain a high degree of parallelism and thus high performance. In this work, we show how a simple arrangement of FPGAs and memory can be used to synthesize a wide variety of image processing pipelines having different topologies and functionality. >
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