Abstract
An algorithm for adaptive differential pulse‐code modulation (ADPCM) has been implemented in real time on a Bell Laboratories produced digital signal processing integrated circuit [J. S. Thompson and J. R. Boddie, IEEE ASSP Conference, Denver (April 1980)]. The algorithm demonstrates the flexibility and programability of the IC processor for doing medium‐scale signal processing. The processor can decode an instruction, fetch data, and perform a 16‐bit by 20‐bit multiplication and a full 36‐bit product accumulation in one machine cycle of 800 ns. An 8‐kHz, 4‐bit, ADPCM coder and decoder have been implemented for simultaneous operation, consuming approximately one‐half of the processor's capability. General details of the IC architecture and the adaptation of the ADPCM algorithm to this architecture will be discussed.
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