Realizing a security aware triple modular redundancy scheme for robust integrated circuits

Abstract

Hardware Trojans are malicious alterations in Integrated Circuits (ICs) which are covertly inserted by third party IC manufacturers. Hardware Trojans can leak confidential information or disable the entire IC. The detection of these Trojans is performed through logic or side channel based testing. The detection sensitivity of these methodologies depends on the placement and the size of the Trojans. In this work, we present a probabilistic model for ICs that produces useful diagnostic results to understand the placement of the stealthiest Trojans. Using this information, we propose a selective Triple Modular Redundancy (TMR) scheme to mask the effect of Trojans along with transient errors, thereby realizing a security aware reliability model. The diagnostic results from the presented Probabilistic Model (PM) provide helpful information for TMR placement that can address the effects of both Trojan and transient error on the primary outputs. We show that for a given circuit with random input probability distribution, the unpredictable equally probable outputs which are vulnerable to errors will also be vulnerable to Trojans. Therefore for both security and reliability, we propose that TMR should be implemented on the paths that lead to equally probable primary outputs. The presence of TMR either forces the adversary to place the Trojan on the path leading to biased outputs or to place at least two copies of the Trojan on the path leading to equally probable outputs. The former will increase the detection sensitivity for logic based testing, and the later will increase the detection sensitivity for side channel based testing.