Realization of the SISO Architecture for PBCH of 3GPP-LTE using PlanAhead Tool and Virtex-5 Device

Abstract

Wireless network has been improved after 3G by means of higher data rates with better coverage and by reducing latency. LTE is the technology that provides backward compatibility with 3G and 4G technologies. Compared with 3G, it offers high data rates of the order of 50Mbps for uplink and 100Mbps for downlink. LTE is able to provide services in scalable bandwidth (1.4, 3, 5, 10, 15 or 20 MHz). It uses the frame structure as Time Division Duplexing (TDD) and Frequency Division Duplexing (FDD). LTE technology uses different channels in both links for different applications. This paper mainly focuses on downlink channels, particularly data channels named as PDSCH, PBCH and PMCH. The main objective of this paper is the realization of the SISO (Single Input- Single Output) architecture of PBCH downlink data channel with its own transmitter and receiver. Information is processed at transmitter by means of scrambling, modulation, layer mapping, precoding and mapping to resource elements. Similar to the transmitter, receiver also has to perform some techniques to retrieve the original data such as demapping from resource elements, decoding, delayer mapping, demodulation and descrambling. Simulation of these steps for transmitter is done by using ModelSim 6.4a and the synthesis and implementation are done by using PlanAhead 13.2 virtex-5, xc5vlx50tff1136-1 board. Power estimation, resource estimation, RTL designs and FPGA editors are shown for the transmitter and receiver structure.