Realization of sequential reversible circuit from finite state machine

Abstract

Reversible logic has emerged as a promising technology for low power and high speed computations. However the realization of sequential circuit in reversible logic is still at premature stage. One of the traditional ways of specifying sequential circuit functionality is using Finite State Machine (FSM). The techniques for obtaining conventional irreversible circuits from FSM are well established. The generation of reversible circuits using FSM is very difficult because of the fact that FSM may not be reachable to a unique stage by reversing the transition. A very few attempts have been reported in the literature for the conversion FSM to reversible FSM. To the best of our knowledge, this is the first attempt for realizing sequential reversible circuit using reversible FSM. It was observed that the attempt made in [1] for generating reversible FSM from traditional (original) FSM were not suitable for generating sequential reversible circuit. This paper has improved the generation of reversible FSM and evolved the step by step procedure to generate the sequential reversible circuit from reversible FSM. We have verified our method by generating sequential reversible circuit of string accepter and odd parity generator. Because of non-availability of generated sequential reversible circuit in literature, our results cannot be compared with any other circuits. We expect that the sequential reversible circuits will help in debugging the reversible circuits, handling the ambiguous state of an FSM and generating the original input in reverse direction by reversing the original output. We hope this paper will enhance the research in the field of reversible sequential circuit.