Abstract
Realization of transmitter and receiver architecture for LTE is the major research work being carried out by implementation experts. There are four Control channels available in LTE for both uplink and downlink. The uplink control channel is PUCCH. The downlink control channels are PDCCH, PCFICH and PHICH. The Physical Hybrid Automatic Repeat Request (ARQ) Indicator Channel(PHICH) is the control channel which carries the acknowledgement (ACK/NACK), denoted as Hybrid ARQ Indicator(HI).These control channels play a key role in the correct decoding of the payload information. The HI is used to indicate the ACK for data sent using Physical Uplink Shared Channel (PUSCH), and is important for the system performance. In this paper, the realization of architecture for the PHICH are done using FPGA, where the main aim is to estimate the HI correctly in the receiver side. The simulations are done using Modelsim and are implemented in Xilinx Spartan 3E kit.
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