Realization of multiprocessing on a RISC-like architecture

Abstract

A processor in a multiprocessor environment must be able to tolerate memory latency and handle synchronization efficiently. Multithreaded execution is a technique which can support not only multiprocessing directly at the architecture level, but aso hiding memory latency by using parallelism in multiprocessor environments. In this paper, we present a processor architecture MTMA that combines the RISC- and multithreaded properties. Instead of tagged memory and its complex control logic, we use queue-based operations as primitives for synchronization of different threads and other issues. It has been shown that our approach can reduce the complexity of hardware implementation greatly. Furthermore, queue-based primitives can also be applicable far beyond synchronization of parallel threads. The MTMA's architecture is simple, hence, it is expected to integrate the architecture on a single chip.