Abstract
The case of low power wide-band analog systems built with CMOS transconductors is addressed. The technique consists of optimizing the performance of a CMOS transconductor for wide-band operation with low dc power consumption. This unfolds the opportunity of realizing analog systems (such as a filter) which minimize the power dissipation for a given bandwidth or maximize the bandwidth for a given dc power consumption. Theoretical analyses leading to the optimal solutions for a specific CMOS transconductor are presented. These results are substantiated by HSPICE simulation for a 0.8-/spl mu/m BiCMOS process. The application of the technique is illustrated by considering realization of several gm-C biquadratic filters and the tradeoff between power dissipation and operating bandwidth is discussed. The results are important because of recent interests in low-power wide-band CMOS VLSI systems.
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