Realization of a novel on-site coding digital beamformer using FPGAs

Abstract

Summary form only given: Ultra-wideband (UWB) systems with digital beam forming are essential to realizing cognitive and software defined radios. Concurrently, advances in digital signal processing hardware and algorithms have allowed for increased data rate handling, large memory blocks, and adaptivity. Therefore, these digital back-ends have drastically reduced the complexity of digital beamforming. Consequently, techniques such as monopulsing, multiple beams and null steering can be employed for phased arrays and MIMO based antennas. Even more important is the realization of beam forming across large, nearly 10:1, bandwidths as is the case here. A novel on-site coding receiver (OSCR) architecture was recently proposed to significantly reduce the intense hardware and power requirement for digital beamforming [Alwan et. al., Springer, 2013]. More specifically, the proposed OSCR employs a code division multiplexing (CDM) technique and a single ADC serving a group of array elements. The latter concept significantly reduces power requirements as it eliminates the need for a single ADC serving each antenna element. Instead, we employ CDM prior to combining the signal paths into a single ADC. The employed CDM technique amounts to mixing each signal with a unique orthogonal Walsh-Hadamard code. These codes serve to identify the signal as associated with a specific antenna element. At the digital back-end, code decorrelation must be carried out to recover the signal associated with each array element path. In this paper, we present a four channel hardware implementation of the proposed OSCR receiver integrated with a FPGA design for digital beamforming. The aforementioned encoding/decoding is accomplished using the Virtex 7 family: XC7VX485T series FPGAs through VHDL codes and external clock synchronization. As part of the proposed back-end, digital filtering is performed on the decorrelated signals to retrieve the desired signal(s). The necessary phase to each signal path is applied during the latter step. To achieve the aforementioned FPGA functionality, Xilinx ISE is used for programming, testing and simulation. More details about the hardware receiver realization with demonstrations on SNR measurements and phase error evaluations will be presented in the conference.