Realization of 8x8 Memory Array using Optimized NVSRAM Cell

Abstract

The Static Random-Access Memory (SRAM) is the fundamental block in the larger memories. The SRAM memories are widely used because of its lower power consumption and delay. The SRAM memories are used in Cache memories. So, the delay of the circuit should be very less. The Non-Volatile memories are getting greater attention due to its Non-Volatile property. The circuits should have larger immunity to noise voltages. So, the Static Noise Margin (SNM) of the circuits should be very high. In this paper, the VTEAM model based Memristor has been designed. The 7T1M Non-Volatile SRAM (NVSRAM) has been proposed for the higher SNM value. The proposed 7T1M NVSRAM cell and existing 7T2M NVSRAM cell has SNM values of 0.518V and 0.04V respectively. The Average Restore time of 7T1M NVSRAM is decreased by 66% when compared to the 7T2M NVSRAM Cell. The different peripheral components like Write driver circuit, Precharge circuit, Row and Column Decoder and Sense Amplifier have been designed. The 8x8 Non Volatile Memory array has been designed using the proposed 7T1M NVSRAM cell and peripheral circuits. All the design is done using the Cadence Virtuoso tool at 45 nm technology with an operating voltage of 1.2 V.