Realization method of totally shelf—Checking error checking and correcting circuits for main memory systems

Abstract

AbstractThis paper proposes a realization method for totally self‐checking ECC (Error Correcting and Checking) circuits using SEC‐DED (Single‐Error‐Correcting and Double‐Errors‐Detecting) codes. The methods of constructing self‐checking ECC circuits are divided into two categories: the method of constructing them as a whole; and the method of adding a redundant circuit for each functional circuit. Up to now, the former conventional method has had such problems as the number of gates being too large and the fault‐detectability being insufficient. These problems can be solved by adding one checker circuit for the ECC circuits in this paper. First, we design the new odd‐weight‐column H‐matrix which has the ability of SEC‐DED codes. Then the syndrome generator, the syndrome decoder, and one parity tree checker circuit are constructed based on this H‐matrix. Furthermore, this proposed method can distinguish a stuck‐at fault in ECC circuits from errors in the main memory. The increasing rate of gates to realize totally self‐checking ECC circuits is about 37 to 56% for the information‐bit length k = 16‐64 bits. This is smaller by about 5% than the best method of adding redundant circuit for each functional circuit.