Realization and Optimization of Combinational Circuits Using Simulated Annealing and Partitioning Approach

Abstract

Combinational logic circuits (CLCs) are basic building blocks of a system and optimization of these circuits in terms of reduced gates, transistors, or levels will lead to reduced area on chip, reduced power, and improved speed. Simulated annealing (SA) is a thermo-inspired metaheuristic used for solving various engineering and non-engineering problems. SA is also used for the realization and optimization of CLCs. Circuits with a large number of inputs and outputs require more generations for realization. Realization of the optimal circuit with fewer generations is desired as realization time increases with increase in the number of generations. In this paper, an attempt is made to realize circuits using population-based SA with fewer generations. SA with partitioning approach is proposed in this paper for circuits that could not be realized with fewer preset generations. To evaluate the performance of the proposed work, benchmark circuits from LGSynth'91 are considered, and it is observed that the success rate improved and realization time reduced with the proposed partitioning approach. During the evaluation, it is also observed that the gate count was reduced by 2.5–77.39% and the transistor count was reduced by 7.69–95.53% on using proposed work with fewer generations over circuits reported in the literature.