Realistic scaling scenario for sub-100nm embedded SRAM based on 3-dimensional interconnect simulation

Abstract

It is still an open problem to elucidate the scaling merit of the embedded SRAM with the Low Operating Power (LOP) MOSFET's fabrication in 50, 70 and 100nm CMOS technology node. Taking into account the realistic SRAM cell layout, we evaluate the parasitic capacitance of Bit Line (BL) as well as Word Line (WL) in each generation. By means of 3-Dimensional (3D) interconnect simulator (Raphael), we focus on the scaling merit through the comparison of the simulated SRAM BL delay in each CMOS technology node. In this paper, we propose two kinds of original interconnect structures which add some modifications to ITRS, and clarify for the first time that the original interconnect structures guarantee the scaling merit of the SRAM cell fabricated with the LOP MOSFET's in 50 70 and 100nm CMOS technology node.