Abstract
Multistage switches have been used as ATM switching fabrics in broadband ISDN networks, and also to connect processors to memories in massively parallel multiprocessor systems. Previous performance models for multistage switches have been neither accurate enough nor based on realistic assumptions regarding modelling the correlation of the blocked packets in successive stages of the switch. Two new analytical models for accurate analysis of multistage switches are proposed. The new models reflect the realistic behaviour of blocked packets, and take into account the fact that a blocked packet always hunts for the same output link in successive clock cycles. The results obtained from the models are more accurate than those available in the literature.
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