Realiability Characteristics of Metal/High-K Pmos with Top Interface Engineered Band Offset Dielectric (BOD)

Abstract

Implementation of high dielectric constant material, HfSiON, by the 32 nm node will require a demonstrated controllability of threshold voltage (VTH) by the use of a metal with a band-edge effective work function. However, there have been difficulties in identifying a metal gate that appropriately shifts the threshold voltage accordingly. One possible scheme for PMOS band-edge metals is engineering the metal/dielectric interface. This phenomenon has been utilized in memory application according to W.H. Lee et al. (1997) and J.H. Klootwijk et al.(1999), but threshold voltage tuning using band offset engineering is a new approach. In this report, we show that using aluminum oxide as the engineered interface drastically reduces threshold voltage (despite an increase in equivalent oxide thickness). Furthermore, once a viable scheme such as this has been identified, it still must undergo full rigorous reliability screening before it can be properly implemented in any application. We further show that this PMOS metal gate scheme has no deleterious affects on negative bias temperature instability (NBTI) and time-dependent dielectric breakdown (TDDB) such that scaling of the dielectric for 32 nm applications is possible