Real-Time FPGA-Based Detection of Speeded-Up Robust Features Using Separable Convolution

Abstract

In this paper, we propose a novel architecture for efficient detection of speeded-up robust features (SURF) for field-programmable gate array (FPGA). The main benefits of the proposed architecture are in real-time low-latency performance and scalability. The proposed solution provides a significant acceleration of salient points extraction that is fundamental image processing technique for vision-based methods including the simultaneous localization and mapping. Based on the presented practical results, the proposed architecture is capable of processing streaming image data at the rate of 140 Megapixels per second that roughly scales from the 640 $\times$ 480@420 fps up to 1920 $\times$ 1080@60 fps video streams on a low-end, low-cost FPGA solution (Cyclone V). Moreover, the proposed feature detection utilizes only about 20% of logic elements of the FPGA which supports further parallel processing of multiple inputs.