Real-time architecture for channel estimation and equalization in broadband PLC

Abstract

Broadband Power Line Communications (PLC) is an attractive area for providing broadband access in facilities where mains are already deployed, such as factories, buildings, houses, etc. In such systems, the design of efficient algorithms for synchronization, channel estimation and equalization is of great importance for reliable communications. Although there is a large amount of research done in channel estimation and equalization for wireless communication systems, the PLC channel has particular features that prevent from directly applying the techniques often used in wireless systems. In this way, PLC channels commonly present frequency selective fading, impulsive noise and coloured noise. Furthermore, some previous algorithms have effectively dealt with undesired channel effects but they imply a high computational complexity and cost, thus limiting their practical applicability. This work proposes real-time FPGA-based (Field-Programmable Gate Array) architecture, designed to implement channel estimation and equalization in broadband PLC. The approach is based on a Wavelet-OFDM (Orthogonal Frequency Division Multiplexing) modulation, also known as FBMC (Filter Bank Multi-Carrier), where cross-correlation techniques have been applied on the Zadoff-Chu sequences used as pilot signals or preambles. The architecture has been implemented in a Xilinx XC7K325T FPGA, and experimental tests in a lab environment successfully show that the proposal can effectively recover the transmitted signals.