Readout chip with RISC-V microprocessor for hybrid pixel detectors

Abstract

Hybrid single-photon counting pixel detectors have recently been widely used for X-ray and ionizing particle detection in medicine, high-energy physics, and material science. Many different chips have been developed for the readout of the semiconductor pixel sensor. Typically, developed ASICs have very limited digital logic and do not provide substantial data processing. In this paper, we present the readout chip that integrates the readout channels matrix with a RISC-V-based microprocessor SoC. The designed device has been prototyped in an FPGA and sent to production in a CMOS 40 nm process. Integration of a pixel matrix with the RISC-V-based central processing unit significantly improved the detector functionality. It enabled the device to work independently without external assistive device usage and execute many algorithms, e.g., calibration, threshold scanning, and data filtering, on-chip. Communication between the CPU and the pixel matrix was carried out through the dedicated Pixel Matrix Controller with the CPU standard I/O operations usage. This specialized peripheral consists of a coprocessor responsible for precise matrix control, a data converter for data conversion acceleration, and control and status registers connected to the core data bus. Many algorithms have been developed and tested, one of which is the intelligent real-time filtering of regions of interest.