Abstract
Hardware accelerator has been reported for implementing ray tracing to achieve high realism in 3D graphics rendering based on Central Processing Unit (CPU), Graphic processing Unit (GPU) and Application Specific Integrated Circuit (ASIC) technology. In this paper, a novel hardware structure for ray tracing is proposed, and implemented in single Field Programmable Gate Array (FPGA) with Hard Processor System (HPS). Control rendering algorithm is arranged on HPS side. The loop unrolling and pipelining design on FPGA side accelerates the numerical differentiation methods and the ray-object intersection algorithm. The design is simplified and implemented on an Intel Cyclone V device, which can quickly complete algorithm expansion and verification with Open Computing Language (OpenCL). The experiment result shows that the design, working with a clock rate of 50MHz, achieves 2.8 million rays per second on single FPGA system.
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