RASA: Reliability-Aware Scheduling Approach for FPGA-Based Resilient Embedded Systems in Extreme Environments

Shakaiba Majeed,Klaus McDonald-Maier,Shoaib Ehsan,Sangeet Saha,Xiaojun Zhai

doi:10.1109/tsmc.2021.3077697

Abstract

Field-programmable gate arrays (FPGAs) offer the flexibility of general-purpose processors along with the performance efficiency of dedicated hardware that essentially renders it as a platform of choice for modern-day robotic systems for achieving real-time performance. Such robotic systems when deployed in harsh environments often get plagued by faults due to extreme conditions. Consequently, the real-time applications running on FPGA become susceptible to errors which call for a reliability-aware task scheduling approach, the focus of this article. We attempt to address this challenge using a hybrid offline-online approach. Given a set of periodic real-time tasks that require to be executed, the offline component generates a feasible preemptive schedule with specific preemption points. At runtime, these preemption events are utilized for fault detection. Upon detecting any faulty execution at such distinct points, the reliability-aware scheduling approach, RASA, orchestrates the recovery mechanism to remediate the scenario without jeopardizing the predefined schedule. Effectiveness of the proposed strategy has been verified through simulation-based experiments and we observed that the RASA is able to achieve 72% of task acceptance rate even under 70% of system workloads with high fault occurrence rates.

Highlights

I N THE last couple of decades, field-programmable gate arrays (FPGAs) have found widespread use in embedded applications ranging from avionics to automotive, and object tracking [1] to cryptography [2]
The internal architecture of FPGA has been assumed to be similar to that of the Xilinx Virtex series of FPGAs [32]. These FPGAs consist of a two-dimensional array of configurable logic blocks (CLBs) with components, such as multipliers (MULs) blocks, block RAMs (BRAM), clocks (CLKs), I/O blocks (IOBs), etc
1) Task Success Ratio Versus System Utilization: Fig. 6 depicts the Task success ratio (TSR) achieved by reliabilityaware scheduling approach (RASA) on a 4-tile and 8-tile FPGA, respectively (M = 4 and 8) for the varying values of system utilization (Sysuti)

Summary

INTRODUCTION

I N THE last couple of decades, field-programmable gate arrays (FPGAs) have found widespread use in embedded applications ranging from avionics to automotive, and object tracking [1] to cryptography [2]. An FPGA-based embedded system for a robot demands well-defined scheduling methodologies, feasibility criteria, and admission control mechanisms for real-time task sets that are being executed. In the case of fully reconfigurable systems, the main hurdle becomes the reconfiguration event which has to be synchronous for an entire FPGA and consumes huge reconfiguration overhead and exhibits less efficiency This is not suitable for real time and continuous operation as required by robots. To solve this problem, this work presents a methodology for the reliable scheduling technique for a set of safety-critical periodic tasks on runtime partially reconfigurable platforms.

RELATED WORK

Architecture Model

Application Model

Fault Model

Fault-Tolerance Mechanism

RASA ALGORITHM

OFrg: Full Reconfiguartion Overhead

RELIABILITY MODELING

EXPERIMENTAL SETUP

VIII. RESULTS AND ANALYSIS

Evaluation of RASA-Offline

Evaluation of RASA-Online