Abstract
AbstractRapid thermal annealed (RTA) bilayers of TiW/Ti were evaluated for contact metallization in advanced VLSI Si circuits. It was found that RTA and a minimum thickness of Ti are necessary to achieve consistently low + contact resistance. RTA has little effect on n+ and polysilicon contact resistances. With RTA, TiSi2 is formed at the Ti/Si interface and a thin nitrogen—containing layer is formed on the TiW surface. By controlling RTA temperature and time, the interaction between Si and TiW during RTA could be minimized while the gain factor of p—channel MOSFETs was not degraded. Moreover, the leakage currents of n+ and p+ contact chains did not increase after 30 minute anneals up to 525C.
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