Rapid prototyping of etch test structures for hard mask development using electron beam lithography

Abstract

Semiconductor manufacturing depends on the development of new processes, advanced patterning, and novel materials to create smaller and higher performing devices to follow the industry roadmaps for applications for computing and systems (such as smartphones and servers). For dynamic random access memory (DRAM) applications, the biggest efforts are engaged in scaling and shrinking of the nodes, and these then affect the area density, performance, and cost of the DRAM cells. However, while we are reaching a slowdown in dimension-scaling, more innovation is needed to sustain the high aspect ratios required in the capacitor’s architecture—whether it is moving toward 3D architectures or developing new materials to sustain the challenge of scaling. To accelerate the learning, it is essential to screen novel hard mask (HM) materials in a rapid fashion to speed their development. While EUV (extreme ultraviolet—a wavelength of 13.5 nm) lithography requires 300 mm wafers, electron beam lithography (EBL) generates nanoscale patterns in a maskless manner on smaller substrates (from 300 mm wafers to 10 mm2 coupons) mimicking sub-50 nm EUV features. The primary goal of this work is to create a path for rapid screening of HM materials that are still under early phase development and which are prepared in small chamber tools (coupon chambers) and, therefore, not ready for 300 mm process integration. While the features investigated of 44 nm half pitch seem extremely reasonable for e-beam, the requirements and the approaches used to address the needed patterned area, resolution, speed, and uniformity exceed the standard conditions previously reported in the literature. Each aspect will be evaluated in the context of a “dots on the fly,” or DOTF, patterning technique.