Abstract
Managing the power in highly-integrated systems on chips becomes inevitable in modern designs. Complex systems require complex power management, and it is always difficult to determine whether the designed power management is the most efficient. In our previous work, we have proposed a simplified power-management specification method at the system level of abstraction. In this paper, we propose a system-level power-management evaluation approach that enables a designer to explore various power-management designs in a short time and select the best. The proposed exploration method is easy-to-use and can be used to speed-up the low-power systems development.
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